1. Field of the Invention
The present invention relates to a bipolar semiconductor integrated circuit having an improved element layout pattern and an improved circuit constitution.
2. Description of the Related Art
In bipolar semiconductor integrated circuits in which the individual elements are isolated by PN-junctions, a PNP- or an NPN-junction region is developed between a transistor and an adjacent transistor. When equivalently viewed, therefore, the integrated circuit containing a transistor formed of an isolation region and of parts of elements on both sides thereof. Depending upon the voltage applied to the circuit, therefore, there appears a parasitic element, such as a parasitic transistor, which gives rise to the operation of the occurrence of a parasitic effect which is detrimental to the semiconductor circuit.
Japanese Examined Patent Publication (Kokoku) No. 4-67787 discloses a bipolar integrated circuit in which the active elements are isolated by a PN-junction, and wherein an output-stage transistor is disposed on one side and a control transistor is disposed on the other side with a current-feeding transistor that feeds current to the output-stage transistor sandwiched therebetween without increasing the chip area of the semiconductor integrated circuit. The interposed current-feeding transistor helps suppress the parasitic effect caused by a parasitic element that appears between the control transistor and the output-stage transistor.
However, when a negative potential is applied to the output-stage transistor, such as when a load is being driven by a motor, the parasitic effect is not sufficiently decreased depending upon the patterned arrangement of the output-stage transistor, current-feeding transistor and control circuit transistor formed on the semiconductor. The can result in the occurrence of erroneous operation.
FIG. 12 illustrates changes in a motor terminal voltage (VM) and in a motor current (IM) with the passage of time of as a DC motor is driven. A negative current is generated when the motor that was running comes to a halt and a corresponding negative voltage is generated across the output-stage transistor. The negative current can be several hundred milliamperes in the case of a motor mounted on a vehicle. In such a case, erroneous operation is likely to take place as described above.
The object of the present invention is, therefore, to suppress the parasitic effect and to eliminate erroneous operation even when a negative potential is applied such as when a load is being driven a motor controlled by a bipolar semiconductor integrated circuit.